A flash memory that is widely used as a nonvolatile memory is the electrically erasable programmable read only memory (EEPROM). Such a flash memory can program and erase data electrically.
That is, in a program operation, a threshold voltage of a cell transistor is elevated by forming hot electrons in a drain and accumulating the hot electrons in a floating gate.
In an erase operation, the threshold voltage of the cell transistor is lowered by generating a high voltage between a source and the floating gate through the F-N (Fowler-Nordheim) tunneling and thus emitting the electrons accumulated in the floating gate.
Meanwhile, to achieve high integration of memory semiconductor devices, research and development for decreasing the area of the cell transistor and accomplishing a low operation voltage have been actively performed. Flash memories increase static capacitances by using NO (nitride-oxide), ONO (oxide-nitride-oxide) or other high dielectrics as an intergate dielectric layer instead of silicon dioxide (SiO2).
In a process of manufacturing a cell transistor of a flash memory using an intergate dielectric layer of an ONO structure, the ONO structure is generally formed by growing a dielectric layer on a polycrystalline silicon (hereinafter, referred to as ‘polysilicon’) layer used as a floating gate through a high temperature thermal oxidation.
Then, to form the polysilicon layer used as the floating gate, a deposition process should be performed at a high temperature.
In the case where such a flash memory device is formed inside a flat panel display device, such a high temperature deposition process may cause a problem.
Research on nonvolatile semiconductor memory (NVSM) devices, which are applicable to flat panel display devices requiring low power consumption, have been actively performed in recent years.
A flat panel display device includes a transparent glass substrate, a thin film transistor (TFT) array and various driving elements, and displays an image on the transparent glass substrate by manipulating the above elements.
In the case where a process for forming a high temperature polysilicon layer is performed on the transparent glass substrate, the glass substrate may be melted and can fail.
To solve the above problem, an amorphous silicon layer is formed on the glass substrate by a low temperature deposition process and is then crystallized by an Excimer laser annealing process. However, the crystallized polycrystalline silicon layer has an irregular upper surface.
When a tunnel oxide layer is formed on the irregular polycrystalline silicon layer, the tunnel oxide also has an irregular upper surface and a bad layer quality, which deteriorate a program characteristic of the NVSM device.